Latch-up Considerations for ESD Protection Devices on High Speed Serial Interface Applications

Introduction As process geometries of chipsets that drive today’s high speed serial interfaces become smaller and consequently more sensitive to transients such as ESD, the challenge to provide adequate protection for these chipsets is growing. A type of device that exhibits a negative resistance on a portion of their current−voltage characteristic is one solution to overcome the protection challenge. However, when using such a snap-back device, the effect of data line latch−up must be considered. This application note will discuss the effects of a latch−up condition and their applicability to snap-back protection devices. The note will also explain the relevant portions of certain high speed serial interfaces such as HDMI 1.4, USB 2.0, and USB 3.0 with respect to latch-up by analyzing potential latch−up conditions in each case. Based on the analysis, recommendations and design specifications for the protection device will be presented for each case in order to guarantee latch−up free applications. The below recommendations for each case will be discussed in relation to ON Semiconductor’s ESD8000 series technology.